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- 151 - BIOS Setup
Calculate MaxRdLatency per channel 0xA120
TpProcMemReceiveDqsTraining 0xA121
Set Write Data delay 0xA122
Write test pattern 0xA123
Start read sweep 0xA124
Set Receive DQS delay 0xA125
Read Test pattern 0xA126
Compare Test pattern 0xA127
Update results 0xA128
Start Find passing window 0xA129
TpProcMemTransmitDqsTraining 0xA12A
Start write sweep 0xA12B
Set Transmit DQ delay 0xA12C
Write test pattern 0xA12D
Read Test pattern 0xA12E
Compare Test pattern 0xA12F
Update results 0xA130
Start Find passing window 0xA131
TpProcMemMaxRdLatencyTraining 0xA132
Start sweep 0xA133
Set delay 0xA134
Write test pattern 0xA135
Read Test pattern 0xA136
Compare Test pattern 0xA137
Online Spare init 0xA138
Bank Interleave Init 0xA139
Node Interleave Init 0xA13A
Channel Interleave Init 0xA13B
ECC initialization 0xA13C
 0xA13D
Before callout for "AgesaReadSpd" 0xA13E
After callout for "AgesaReadSpd" 0xA13F
Before optional callout "AgesaHookBeforeDramInit" 0xA140
After optional callout "AgesaHookBeforeDramInit" 0xA141
Before optional callout "AgesaHookBeforeDQSTraining" 0xA142
After optional callout "AgesaHookBeforeDQSTraining" 0xA143
Before optional callout "AgesaHookBeforeDramInit" 0xA144
After optional callout "AgesaHookBeforeDramInit" 0xA145
After MemDataInit 0xA146
Before InitializeMCT 0xA147
Before LV DDR3 0xA148
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